1. Field of the Invention
The present invention relates to a semiconductor storage apparatus. More particularly, the present invention relates to a data line array and a data line charging circuit in a semiconductor memory which is applied to, for example, a NOR type flash memory.
2. Description of the Related Art
Nonvolatile semiconductor storage apparatuses capable of electrically programmable data include a flash memory capable of electrically erasing data on a number of memory cells. In the flash memory, a charge quantity of a floating gate of a memory cell transistor is changed by an erasing/writing operation, thereby changing a threshold voltage thereof and storing data. For example, “0” data is stored by discharging electrons of the floating gate to set a threshold voltage to be negative, and “1” data is stored by injecting electrons into the floating gate to set the threshold voltage to be positive. The discharge/injection of electrons is carried out between the floating gate and a semiconductor substrate via a tunnel oxide film.
FIG. 9 is a circuit diagram depicting an example of a portion of a cell array, a data line array, a column selector, and a sense amplifier array of a conventional NOR type flash memory.
A sub-cell array (a region provided by dividing a cell array) is formed on a P-type well region which is physically divided in minimum units of erasure. In a memory space of this array, for example, 128K memory cells (cell transistors) MC are allocated in a matrix.
Drains of the cell transistors MC in the same row are connected to bit lines BL, for example, 128 bit lines BL, correspondingly. Drains of the cell transistors MC in the same column are connected to the same bit line BL. Sources of the cell transistors MC in two rows that are adjacent to each other and form one set of row lines in the column direction are connected to the same source line SL.
Word lines WL, for example, 1024 word lines WL, extend in the row direction, and each of the word lines is connected to gates of memory cells MC, for example, 128 memory cells MC, in the corresponding row. Data writing is carried out at the same time and data readout is also carried out at the same time to 128 memory cells MC in the same row, which corresponds to a selected word line.
One end of each of bit lines BL is connected to a sense amplifier S/A via a column select switch CS and a data line DL. A plurality of data lines DL are arranged to form a data line array DLA, and a load circuit (charging circuit) is connected between one end of each of the data lines DL and a power supply (VDD) node. The column select switch CS is formed of an N-channel metal oxide semiconductor field effect transistor (NMOSFET), and a column decode signal CD is inputted from a column decoder to a gate of the transistor so that a column corresponding to the transistor is selected.
In order to reduce interference between data line arrays DLA, a dummy data line DDL is generally provided between the adjacent data line arrays, as shown in FIG. 10. In such a case, in general, the dummy data line DDL is connected to ground. In FIG. 10, VSS denotes a ground potential; Cside denotes a coupling capacitance which exists between the adjacent data lines DL in the data line array; Cside′ denotes a coupling capacitance which exists between the data line DL at the outermost side of the data line array and the dummy data line DDL; and Cdown denotes a capacitance which exists between each of the data line DL and the ground.
However, the coupling capacitance Cside′ which exists between the data line DL at the outermost side of the data line array and the dummy data line DDL and the coupling capacitance Cside which exists between the adjacent data lines DL in the data line array differs from each other, and thus a capacitance difference exists therebetween. That is, since a potential of the dummy data line DDL adjacent to the data line DL at the outermost side of the data line array is VSS, a coupling capacitance when viewed from the sense amplifier S/A toward the data line side is greater in the case where the data line DL at the outermost side of the data line array is selected in the data read mode than in the case where a data line DL other than that at the outermost side of the data line array is selected in the data read mode. In addition, if the width and thickness of each of the data lines DL in the data line array are different from another one, the coupling capacitance Cside is different according to a combination of the adjacent data lines DL, thus a capacitance difference exists.
When a capacitance difference exists in a coupling capacitance in this way, charge characteristics are different from each other on the basis of the selected data line DL, and a potential rise speed of the data line DL is different from another one. Thus, it has been unavoidable that time is needed until the potential of the data line DL in the data read mode rises close to an equivalent state, after which data determination is made.
On the other hand, when data is read out from a memory cell targeted for readout, a data line DL corresponding to the memory cell and a reference data line (not shown) are selected. However, in order to ensure high speed readout, there is a demand for employing a scheme of sensing data by comparing potentials of the selected data line and reference data line by the sense amplifier S/A in a course of charging the selected data line and reference data line. In this case, as described previously, if charge characteristics are different from each other on a data line basis, there occurs a need for delaying a readout timing according to an electric potential rise of a data line having a large coupling capacitance Cside (data line having a low charge speed), and thus, readout speed is reduced.
As described above, in the conventional NOR type flash memory, there has been a disadvantage that the speed for charging a data line is different from another one depending on a case in which a data line at the outermost side of the data line array is selected in the data read mode and a case where an internal data line of the data line array is selected, and a data readout speed is reduced. In addition, in the case where the width and thickness of each of the data lines in the data line array are not uniform, there has been a disadvantage that a coupling capacitance is different according to a combination of the adjacent data lines in the data line array; a capacitance difference exists; and a data readout speed is reduced. Moreover, discussion relating to a reference data line which is appropriate to read out data contained in the selected data line in the data read mode at a high speed has not been sufficiently made.
A semiconductor integrated circuit described in Jpn. Pat. Appln. KOKAI Publication No. 2001-256789 comprises a memory cell, a plurality of data lines, a sense amplifier, and a dummy data line. The data lines are arranged adjacent to each other and transmit the data read out from the memory cell. The dummy data line is provided along the outside of a data bus line, and a voltage change similar to that of the data line occurs on the dummy data line during a readout operation of the data stored in the memory cell. In the above-described document, there is disclosed that, during the readout operation, due to the similar change of voltage of the dummy data line, an accumulation quantity of a charge for a parasitic capacitance formed between the data line and the dummy data line becomes minimal, and variants in rise time of the plurality of data lines is reduced, so that a readout time (access time) is shortened. However, there is no disclosure relating to a relationship between a data line and a reference data line.